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X28HC64
System Considerations
Because the X28HC64 is frequently used in large memory
arrays, it is provided with a two-line control architecture for
both read and write operations. Proper usage can provide
the lowest possible power dissipation, and eliminate the
possibility of contention where multiple I/O pins share the
same bus.
To gain the most benefit, it is recommended that CE be
decoded from the address bus, and be used as the primary
device selection input. Both OE and WE would then be
common among all devices in the array. For a read
operation, this assures that all deselected devices are in
their standby mode, and that only the selected device(s)
is/are outputting data on the bus.
Because the X28HC64 has two power modes, standby and
active, proper decoupling of the memory array is of prime
concern. Enabling CE will cause transient current spikes.
The magnitude of these spikes is dependent on the output
capacitive loading of the I/Os. Therefore, the larger the array
sharing a common bus, the larger the transient spikes. The
voltage peaks associated with the current transients can be
suppressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recommended
that a 0.1μF high frequency ceramic capacitor be used
between V CC and V SS at each device. Depending on the
size of the array, the value of the capacitor may have to be
larger.
In addition, it is recommended that a 4.7μF electrolytic bulk
capacitor be placed between V CC and V SS for each eight
devices employed in the array. This bulk capacitor is
employed to overcome the voltage droop caused by the
inductive effects of the PC board traces.
1.4
5.5V CC
1.4
1.2
1.0
0.8
0.6
0.4
- 55°C
+ 125°C
+ 25°C
1.2
1.0
0.8
0.6
0.4
5.5V CC
5.0V CC
4.5V CC
0.2
0M
10M
20M
0.2
0M
10M
20M
FREQUENCY (Hz)
FIGURE 10. NORMALIZED I CC (RD) BY TEMPERATURE
OVER FREQUENCY DATA PROTECTION
8
FREQUENCY (Hz)
FIGURE 11. NORMALIZED I CC (RD) @ 25% OVER THE V CC
RANGE AND FREQUENCY
FN8109.2
August 28, 2009
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